PM0056 datasheet(26/156 Pages) STMICROELECTRONICS

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The Cortex-M3 processor

PM0056

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2.2.2

Memory system ordering of memory accesses

For most memory accesses caused by explicit memory access instructions, the memory

system does not guarantee that the order in which the accesses complete matches the

program order of the instructions, providing this does not affect the behavior of the

instruction sequence. Normally, if correct program execution depends on two memory

accesses completing in program order, software must insert a memory barrier instruction

between the memory access instructions, see Section 2.2.4: Software ordering of memory

accesses on page 27.

However, the memory system does guarantee some ordering of accesses to Device and

Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs

before A2 in program order, the ordering of the memory accesses caused by two

instructions is:

2.2.3

Behavior of memory accesses

The behavior of accesses to each region in the memory map is:

Table 11. Ordering of memory accesses(1)

1. - means that the memory system does not guarantee the ordering of the accesses.

< means that accesses are observed in program order, that is, A1 is always observed before A2.

Normal access

Device access

Strongly ordered

access

Non-shareable

Shareable

Normal access

Device access,

non-shareable

Device access, shareable

Strongly ordered access

Table 12. Memory access behavior

Address

range

Memory

region

Memory

type

Description

0x00000000- 0x1FFFFFFF Code

Normal(1)

Executable region for program code.

You can also put data here.

0x20000000- 0x3FFFFFFF SRAM

Normal(1)

Executable region for data. You can

also put code here.

This region includes bit band and bit

band alias areas, see Table 13 on

page 28.

0x40000000- 0x5FFFFFFF Peripheral

Device(1)

XN(1)

This region includes bit band and bit

band alias areas, see Table 14 on

page 28.

0x60000000- 0x9FFFFFFF

External

RAM

Normal(1)

Executable region for data.

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