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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0056 датащи(PDF) 89 Page - STMicroelectronics |
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PM0056 датащи(HTML) 89 Page - STMicroelectronics |
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89 / 156 page  DocID15491 Rev 5 89/156 PM0056 The Cortex-M3 instruction set 3.8.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: • ‘cond’ is an optional condition code, see Conditional execution on page 57. • ‘Rd’ is the destination register. • ‘Rn’ is the source register. • ‘lsb’ is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. • ‘width’ is the width of the bitfield and must be in the range 1 to 32-lsb. Operation BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are unchanged. BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged. Restrictions Do not use SP and do not use PC. Condition flags These instructions do not affect the flags. Examples BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11 from R2 3.8.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width |
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