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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0056 датащи(PDF) 115 Page - STMicroelectronics |
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PM0056 датащи(HTML) 115 Page - STMicroelectronics |
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115 / 156 page  DocID15491 Rev 5 115/156 PM0056 Core peripherals Bits 31:N ADDR[31:N]: Region base address field The value of N depends on the region size. The region size, as specified by the SIZE field in the RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. Bits N-1:5 Reserved, forced by hardware to 0. Bit 4 VALID: MPU region number valid Write: 0: MPU_RNR register not changed, and the processor: –Updates the base address for the region specified in the RNR – Ignores the value of the REGION field 1: the processor: – updates the value of the RNR to the value of the REGION field – updates the base address for the region specified in the REGION field. Read: Always read as zero. Bits 3:0 REGION[3:0]: MPU region field For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR register. |
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