PM0056 datasheet(113/156 Pages) STMICROELECTRONICS

113 / 156 page

DocID15491 Rev 5

113/156

PM0056

Core peripherals

4.2.7

MPU region number register (MPU_RNR)

Address offset: 0x08

Reset value: 0x0000 0000

Required privilege: Privileged

The MPU_RNR register selects which memory region is referenced by the MPU_RBAR and

MPU_RASR registers.

3029

Reserved

PRIVD

EFENA

HFNMI

ENA

ABLE

Bits 31:0

Reserved, forced by hardware to 0.

Bit 2

PRIVDEFENA: Enable privileged software access to default memory map.

0: If the MPU is enabled, disables use of the default memory map. Any memory access to a

location not covered by any enabled region causes a fault.

1: If the MPU is enabled, enables use of the default memory map as a background region for

privileged software accesses.

Note: When enabled, the background region acts as if it is region number -1. Any region that

is defined and enabled has priority over this default map.

If the MPU is disabled, the processor ignores this bit.

Bit 1

HFNMIENA: Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.

When the MPU is enabled:

0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the

value of the ENABLE bit

1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.

Note: When the MPU is disabled, if this bit is set to 1 the behavior is unpredictable.

Bit 0

ENABLE: Enables the MPU

0: MPU disabled

1: MPU enabled

3029

Reserved

REGION[7:0]

PM0056 датащи(PDF) 113 Page - STMicroelectronics

PM0056 датащи(HTML) 113 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL