PM0056 datasheet(111/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

In STM32 implementations, the shareability and cache policy attributes do not affect the

system behavior. However, using these settings for the MPU regions can make the

application code more portable. The values given are for typical situations.

Note:

The MPU attributes don't affect DMA data accesses to the memory/peripherals address

spaces. therefore, in order to protect the memory areas against inadvertent DMA accesses,

the MPU must control the SW/CPU access to the DMA registers.

4.2.5

MPU type register (MPU_TYPER)

Address offset: 0x00

Reset value: 0x0000 0800

Required privilege: Privileged

The MPU_TYPER register indicates whether the MPU is present, and if so, how many

regions it supports.

Table 38. Memory region attributes for STM32

Memory region

TEX

Memory type and attributes

Flash memory

b000

Normal memory, Non-shareable,

write-through

Internal SRAM

b000

Normal memory, Shareable, write-

through

External SRAM

b000

Normal memory, Shareable, write-

back, write-allocate

Peripherals

b000

Device memory, Shareable

3029

Reserved

IREGION[7:0]

rrrr

DREGION[7:0]

Reserved

SEPA

RATE

rrrr

Bits 31:24

Reserved, forced by hardware to 0.

Bits 23:16

IREGION[7:0]: Number of MPU instruction regions.

These bits indicates the number of supported MPU instruction regions.

Always contains 0x00. The MPU memory map is unified and is described by the DREGION

field.

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