AT89LP51RB2 datasheet(61/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

9.2

Interrupt Response

The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls

the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the

preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to

the appropriate service routine as the next instruction, provided that the interrupt is not blocked

by any of the following conditions:

•An interrupt of equal or higher priority level is already in progress

• The instruction in progress is RETI or any write to the IENx, IPLx or IPHx registers

Each of these conditions will block the generation of the LCALL to the interrupt service routine.

The second condition ensures that if the instruction in progress is RETI or any access to IENx,

IPLx or IPHx, then at least one more instruction will be executed before any interrupt is vectored

to. The polling cycle is repeated at the last cycle of each instruction, and the values polled are

the values that were present at the previous clock cycle. If an active interrupt flag is not being

serviced because of one of the above conditions and is no longer active when the blocking

condition is removed, the denied interrupt will not be serviced. In other words, the fact that the

interrupt flag was once active but not serviced is not remembered. Every polling cycle is new.

If a request is active and conditions are met for it to be acknowledged, a hardware subroutine

call to the requested service routine will be the next instruction executed. The call itself takes

four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an

interrupt request and the beginning of execution of the first instruction of the service routine. A

longer response time results if the request is blocked by one of the previously listed conditions. If

an interrupt of equal or higher priority level is already in progress, the additional wait time

depends on the nature of the other interrupt's service routine. If the instruction in progress is not

in its final clock cycle, the additional wait time cannot be more than 4 cycles, since the longest

instruction is 5 cycles long. If the instruction in progress is RETI, the additional wait time cannot

be more than 9 cycles (a maximum of 4 more cycles to complete the instruction in progress, plus

a maximum of 5 cycles to complete the next instruction). Thus, in a single-interrupt system, the

response time is always more than 5 clock cycles and less than 14 clock cycles. See Figure 9-2

and Figure 9-3.

When an interrupt is serviced, its interrupt flag must be cleared before the RETI instruction or

else the interrupt will continue to be generated. Many interrupt vectors have multiple sources.

The service routine normally must determine which flag bit generated the interrupt and that bit

must be cleared by software. If multiple source bits are set for one interrupt, the interrupt will

continue to be generated until all the source bits have been cleared. In some cases the interrupt

flags is cleared by hardware when the interrupt is acknowledged.

The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,

depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-

rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears

the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-

rupt was level activated, then the external requesting source (rather than the on-chip hardware)

controls the request flag. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1,

which are set by a rollover in their respective Timers). When a timer interrupt is generated, the

on-chip hardware clears the flag that generated it when the service routine is vectored to. All

other flags must be cleared by software.

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