AT89LP51RB2 datasheet(53/254 Pages) ATMEL

53 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 7-3.

Brown-out Detector Reset

The AT89LP51RB2/RC2/IC2 allows for a wide V

DD operating range. The on-chip BOD may not

be sufficient to prevent incorrect execution if V

BOD is lower than the minimum required VDD

range, such as when a 5.0V supply is coupled with high frequency operation. In such cases an

external Brown-out Reset circuit connected to the RST pin may be required.

7.3

External Reset

The RST pin of the AT89LP51RB2/RC2/IC2 can function as either an active-low reset input or

as an active-high reset input. The polarity of the RST pin is selectable using the POL pin (for-

merly EA). When POL is high the RST pin is active high with an on-chip pull-down resistor tied to

GND. When POL is low the RST pin is active low with an on-chip pull-up resistor tied to V

DD. The

RST pin structure is shown in Figure 7-4. Entry into reset is completely asynchronous. The pres-

ence of the active reset level on the input will immediately reset the device. A glitch filter will

suppress all reset input pulses of less than 50 ns. Exit from reset is synchronous. In Compatibil-

ity mode the reset pin is sampled every six clock cycles and must be held inactive for at least

twelve clock cycles to deassert the internal reset. In Fast mode the reset pin is sampled every

clock cycle and must be held inactive for at least two clock cycles to deassert the internal reset.

The AT89LP51RB2/RC2/IC2 includes an on-chip Power-On Reset and Brown-out Detector cir-

cuit that ensures that the device is reset from system power up. In most cases a RC startup

circuit is not required on the RST pin, reducing system cost, and the RST pin may be left uncon-

nected if a board-level reset is not present.

Note:

RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external

reset pin is held active. When ISP is disabled by fuse, ISP may only be entered by pulling RST

active during power-up. If this behavior is necessary, it is recommended to use an active-low reset

so that ISP can be entered by shorting RST to GND at power-up.

Figure 7-4.

Reset Pin Structure

VDD

Time-out

VPOR

Internal

Reset

tSUT

VBOD

VCC

DISRTO

WDT Reset

RST

Internal Reset

POL = 1

VCC

DISRTO

WDT Reset

RST

Internal Reset

POL = 0

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