AT89LP51RB2 datasheet(19/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 3-9 and Figure 3-10 show examples of external data memory write and read cycles,

respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle state of

ALE is controlled by DISALE (AUXR.0). When DISALE = 0 the ALE toggles at a constant rate

when not accessing external memory. When DISALE = 1 the ALE is weakly pulled high. DISALE

must be one in order to use P4.4 as a general-purpose I/O. The WS bits in AUXR can extended

the RD and WR strobes by 1, 2 or 3 cycles as shown in Figures 3-13, 3-14 and 3-15. If a longer

strobe is required, the application can scale the system clock with the clock divider to meet the

requirements (See Section 6.8 on page 47).

Notes:

1. WS1 is only available in Fast mode. WS1 is forced to 0 in Compatibility mode.

Table 3-2.

AUXR

– Auxiliary Control Register

AUXR = 8EH

Reset Value = 0000 10X0B

Not Bit Addressable

DPU

WS1(1)

WS0XRS2XRS1XRS0

EXTRAM

Bit

543

Symbol

Function

DPU

Disable Weak Pull-up. When DPU = 0 all I/O ports in quasi-bidirectional mode have their weak pull-up enabled. When

DPU = 1 all I/O ports in quasi-bidirectional mode have their weak pull-up disabled to reduce power consumption.

WS1-0

Wait State Select. Determines the number of wait states inserted into external memory accesses.

WS1

WS0

Wait States

RD / WR Strobe Width

ALE to RD / WR Setup

000

1 x t

CYC (Fast);

3 x t

CYC (Compatibility)

1 x t

CYC (Fast); 1.5 x tCYC (Compatibility)

011

2 x t

CYC (Fast); 15 x tCYC (Compatibility)

1 x t

CYC (Fast); 1.5 x tCYC (Compatibility)

102

2 x t

CYC (Fast)

2 x t

CYC (Fast)

113

3 x t

CYC (Fast)

2 x t

CYC (Fast)

XRS

2-0

XRAM Size. Selects the size of the on-chip extra RAM (EDATA)

XRS2

XRS1

XRS0

EDATA Size (bytes)

Address Range

256

0000H–00FFH

512

0000H–01FFH

010

768 (default)

0000H–02FFH

1024

0000H–03FFH

1152

0000H–047FH

101

Reserved

11–

Reserved

EXTRAM

External RAM Enable. When EXTRAM = 0, MOVX instructions can access the internally mapped portions of the

address space (Extra RAM). Accesses to addresses above internally mapped memory will access external memory. Set

EXTRAM = 1 to bypass the internal memory and map the entire 64KB address space to external memory. The default

state of EXTRAM is set by a user configuration fuse. See Section 24.2 on page 188.

DISALE

ALE Output. When AO = 0 the ALE pulse is active at 1/3 of the system clock frequency in Compatibility mode and 1/2 of

the system clock frequency in Fast mode. When AO = 1 the ALE is inactive (high) unless an external memory access

occurs. AO must be set to use P4.4 as a general I/O.

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