AT89LP51RB2 datasheet(48/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

6.9

Peripheral Clocks

The base peripheral clock is the same as the CPU clock. It is affected by both the X2 setting and

the CKRL prescaler. However, individual peripherals can have their clock further modified using

the Timer Prescaler in the CLKREG register and the clock selection bits in the CKCON0 and

CKCON1 registers. The Timer Prescaler is a 4-bit prescaler controlled by the TPS bits in

CLKREG (See Table 6-8 on page 47). This prescaler is shared among all peripherals and con-

trols the counting rate of Timer 0, Timer 1, Timer 2, the PCA Timer and the Watchdog. By default

the timers will count every CPU clock cycle in Fast mode (TPS = 0000B) and every six CPU

cycles in Compatibility mode (TPS = 0101B).

The bits in CKCON0 and CKCON1 select how the Timer Prescaler affects each peripheral. In

Compatibility mode these bits decide if a further divide-by-two is included in addition to the pres-

caler. This allows a device in X2 mode to use peripherals that still run in X1 mode, i.e. X2 can be

enabled to speed up the CPU without needing to update the peripheral baud rates, overflow

periods, etc. Peripherals not affected by the Timer Prescaler switch between the CPU clock and

the CPU clock divided-by-2.

In Fast Mode the bits in CKCON0 and CKCON1 turn the Timer Prescaler on/off for each periph-

eral. The following equations show the peripheral clock rates in Compatibility Mode and Fast

Mode where ?X2 is a peripherals bit in CKCON0 or CKCON1.

An overview of the peripheral clock selection is given in Figure 6-7 on page 49.

fPERIPHERAL

fCPU

?X2

TPS

()

---------------------------------------------

Compatibility Mode

fPERIPHERAL

fCPU

TPS

---------------------

Fast Mode and ?X2 = 1

Table 6-9.

CKCON0

– Clock Control Register 0

CKCON0 = 8FH

Reset Value = 0000 000?B

Not Bit Addressable

TWIX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

Bit

543

Symbol

Function

TWIX2

Two-Wire Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two

clock periods per peripheral clock cycle (only valid when X2 = 1). In Fast Mode, clear for one system clock period and

set for TPS+1 clocks per peripheral clock cycle. This bit only affects the generated SCL rate during TWI master mode.

WDX2

Watchdog Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for

2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1

clocks per peripheral clock cycle. This bit affects the watchdog timeout period.

PCAX2

Programmable Counter Array Clock. This bit affects the PCA timer increment rate and depends on CPS in CMOD.

CPS1-0 =00B: In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for

2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1

clocks per peripheral clock cycle.

CPS

1-0 =01B: In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock

periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1 clocks per

peripheral clock cycle.

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