AT89LP51RB2 datasheet(69/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

12. I/O Ports

The AT89LP51RB2/RC2/IC2 can be configured for between 36 and 40 I/O pins. The exact num-

ber of general I/O pins available depends on the clock and external memory configuration as

shown in Table 12-1.

Note:

On AT89LP51IC2 OSCB requires 0, 1 or 2 I/O pins depending on the Clock Source B setting. Dis-

abling OSCB (OscbEn = 0) frees up the OSCB pins for general use. Disabling OSCA

(OscAEn = 0) does NOT free up the OSCA pins. OSCA must be configured for Internal RC mode

to use these pins even when running from OSCB only.

12.1

Port Configuration

All port pins on the AT89LP51RB2/RC2/IC2 may be configured in one of four modes: quasi-bidi-

rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port

modes may be assigned in software on a pin-by-pin basis as shown in Table 12-2 using the reg-

isters listed in Table 12-3. The Tristate-Port User Fuse (See Section 24.2 on page 188)

determines the default state of the port pins. When the fuse is enabled, all port pins on P1, P2

and P3 default to input-only mode after reset. When the fuse is disabled, all port pins on P1, P2

and P3 default to quasi-bidirectional mode after reset and are weakly pulled high. P0 always

defaults to open-drain mode. P4.4–5 always default to quasi-bidirectional mode. P4.0–1 always

default to open-drain. The other pins of P4 obey the fuse.

Each port pin also has a Schmitt-triggered input for improved input noise rejection. During

Power-down all the Schmitt-triggered inputs are disabled with the exception of P3.2 (INT0), P3.3

(INT1), RST, P4.6 (XTAL1) and P4.7 (XTAL2). Therefore, P3.2, P3.3, P4.6 and P4.7 should not

be left floating during Power-down. n addition any pin of Port 1 configured as a keyboard inter-

rupt input will also remain active during Power-down to wake-up the device. These interrupt pins

should either be disabled before entering Power-down or they should not be left floating.

Table 12-1.

AT89LP51RB2/RC2 I/O Pin Configurations

Clock Source A

External Program Access

External Data Access

Number of I/O

Pins

External Crystal or

Resonator

Yes (PSEN+ALE+P0+P2)

Yes (RD+WR)

8-bit (ALE+RD+WR+P0)

16-bit (ALE+RD+WR+P0)

External Clock

Yes (PSEN+ALE+P0+P2)

Yes (RD+WR)

8-bit (ALE+RD+WR+P0)

16-bit (ALE+RD+WR+P0+P2)

Internal RC

Oscillator

Yes (PSEN+ALE+P0+P2)

Yes (RD+WR)

8-bit (ALE+RD+WR+P0)

16-bit (ALE+RD+WR+P0+P2)

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