AT89LP51RB2 datasheet(83/254 Pages) ATMEL

83 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 13-4. Timer/Counter 0 Mode 3: Two 8-bit Counters

13.6

Pulse Width Modulation

On the AT89LP51RB2/RC2/IC2, Timer 0 and Timer 1 may be independently configured as 8-bit

asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or

PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the

timer's input pin, T0 or T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0

(P3.4) and T1 (P3.5) must be configured in an output mode. The Timer Overflow Flags and

Interrupts will continue to function while in PWM Mode and Timer 1 may still generate the baud

rate for the UART. The timer GATE function also works in PWM mode, allowing the output to be

halted by an external input. Each PWM channel has four modes selected by the mode bits in

TMOD.

An example waveform for Timer 0 in PWM Mode 0 is shown in Figure 13-5. TH0 acts as an 8-bit

counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is

set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low.

Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to

RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM

output low.

Figure 13-5. 8-bit Asymmetrical Pulse Width Modulation

Control

Interrupt

Control

Interrupt

(8 Bits)

C/T = 0

C/T =1

T0 Pin

GATE0

INT0 Pin

÷TPS

CLKSYS

FFH

00H

RH0

(P3.4)T0

TF0 Set

TH0

time

AT89LP51RB2 датащи(PDF) 83 Page - ATMEL Corporation