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AT89LP51RB2 датащи(PDF) 40 Page - ATMEL Corporation |
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AT89LP51RB2 датащи(HTML) 40 Page - ATMEL Corporation |
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40 / 254 page ![]() 40 3722A–MICRO–10/11 AT89LP51RB2/RC2/IC2 Preliminary • The /DPTR instructions provide support for the dual data pointer features described above (See Section 5.4). •The ASR M, LSL M, CLR M and MAC AB instructions are part of the Multiply-Accumulate Unit (See Section 5.3). • The JMP @A+PC instruction supports localized jump tables without using a data pointer. •The CJNE A, @R i, rel instructions allow compares of array values with non-constant values. • The BREAK instruction is used by the On-Chip Debug system. See Section 23. on page 183. • Some third party assemblers/compilers do not support these instructions. In order to use them you may need to write assembly functions that emulate the instruction by declaring the opcodes inline as shown in Table 5-11. A5 A4 MAC AB Multiply and accumulate 2 9 A5 B6 CJNE A, @R0, rel Compare ACC to indirect RAM and jump if not equal 34 A5 B7 CJNE A, @R1, rel Compare ACC to indirect RAM and jump if not equal 34 A5 E0 MOVX A, @/DPTR Move external to ACC; 16-bit address in alternate data pointer 23/5 A5 E4 CLR M Clear M register 2 2 A5 F0 MOVX @/DPTR, A Move ACC to external; 16-bit address in alternate data pointer 23/5 Table 5-11. Extended Instruction Assembly Emulations Opcode Mnemonic Emulation A5 00 BREAK DB A5H, 00H A5 03 ASR M DB A5H, 03H or DB A5H followed by RR A A5 23 LSL M DB A5H, 23H or DB A5H followed by RL A A5 73 JMP @A+PC DB A5H, 73H or DB A5H followed by JMP @A+DPTR A5 90 MOV /DPTR, #data16 DB A5H followed by MOV DPTR, #data16 A5 93 MOVC A, @A+/DPTR DB A5H, 93H or DB A5H followed by MOVC A, @A+DPTR A5 A3 INC /DPTR DB A5H, A3H or DB A5H followed by INC DPTR A5 A4 MAC AB DB A5H, A4H or DB A5H followed by MUL AB A5 B6 CJNE A, @R0, rel DB A5H, B6H, (LABEL-$-3) where LABEL is the jump target A5 B7 CJNE A, @R1, rel DB A5H, B7H, (LABEL-$-3) where LABEL is the jump target A5 E0 MOVX A, @/DPTR DB A5H, E0H or DB A5H followed by MOVX A, @DPTR A5 E4 CLR M DB E4H, E0H or DB A5H followed by CLR A A5 F0 MOVX @/DPTR, A DB A5H, F0H or DB A5H followed by MOVX @DPTR, A Table 5-10. AT89LP51RB2/RC2/IC2 Extended Instructions Opcode Mnemonic Description Bytes Cycles |
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