AT89LP51RB2 datasheet(6/254 Pages) ATMEL

6 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Note:

1. The AT89LP51IC2 is not available in the PDIP package

Overview

The Atmel

® AT89LP51RB2/RC2/IC2 is a low-power, high-performance CMOS 8-bit 8051 micro-

controller with 24/32 KB of In-System Programmable Flash program memory. The devices are

manufactured using Atmel's high-density nonvolatile memory technology and are compatible

with the industry-standard 80C51 instruction set.

The AT89LP51RB2/RC2/IC2 is built around an enhanced CPU core that can fetch a single byte

from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock

cycles, f o rcing i n str u ctions t o exec u te in 12 , 2 4 or 4 8 c l ock cycles. In the

AT89LP51RB2/RC2/IC2 CPU, standard instructions need only one to four clock cycles providing

six to twelve times more throughput than the standard 8051. Seventy percent of instructions

need only as many clock cycles as they have bytes to execute, and most of the remaining

instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS

throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current con-

sumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a

much lower speed and thereby greatly reducing power consumption and EMI. The

P0.2

I/O

P0.2: User-configurable I/O Port 0 bit 2.

AD2: External memory interface Address/Data bit 2.

ADC2: ADC analog input 2.

P0.1

I/O

P0.1: User-configurable I/O Port 0 bit 1.

AD1: External memory interface Address/Data bit 1.

ADC1: ADC analog input 1.

P0.0

I/O

P0.0: User-configurable I/O Port 0 bit 0.

AD0: External memory interface Address/Data bit 0.

ADC0: ADC analog input 0.

VDD

Supply Voltage

P4.2

I/O

P4.2: User-configurable I/O Port 4bit 2.

XTAL2B: Output from low-frequency inverting oscillator amplifier B (AT89LP51IC2 only). It may

be used as a port pin if the internal RC oscillator or external clock is selected as the clock source

P1.0

I/O

P1.0: User-configurable I/O Port 1 bit 0.

T2: Timer 2 External Input or Clock Output.

XTAL1B: Input to the low-frequency inverting oscillator amplifier B and internal clock generation

circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source

P1.1

I/O

P1.1: User-configurable I/O Port 1 bit 1.

T2EX: Timer 2 External Capture/Reload Input.

SS: SPI Slave-Select.

P1.2

I/O

P1.2: User-configurable I/O Port 1 bit 2.

P1.3

I/O

P1.3: User-configurable I/O Port 1 bit 3.

CEX0: Capture/Compare external I/O for PCA module 0.

P1.4

I/O

P1.4: User-configurable I/O Port 1 bit 4.

SS: SPI Slave-Select (Remap Mode). This pin is an input for In-System Programming

CEX1: Capture/Compare external I/O for PCA module 1.

Table 1-1.

Atmel AT89LP51RB2/RC2/IC2 Pin Description

Pin Number

Symbol

Type

Description

VQFP

VQFN

PLCC

(1)

PDIP

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