AT89LP51RB2 datasheet(33/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

A block diagram of the MAC unit is shown in Figure 5-3. The 16-bit signed operands are pro-

vided by the register pairs (AX,ACC) and (BX,B) where AX (E1H) and BX (F7H) hold the higher

order bytes. The 16-by-16 bit multiplication is computed through partial products using the

AT89LP51RB2/RC2/IC2’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M

accumulator register. The MAC operation is summarized as follows:

All computation is done in signed two’s complement form.

Figure 5-3.

Multiply–Accumulate Unit

The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. This

two-byte instruction requires nine clock cycles to complete as the multiply is done in a sequential

manner using partial products. The operand registers are not modified by the instruction and the

result is stored in the 40-bit M register. MAC AB also updates the C and OV flags in PSW. C rep-

resents the sign of the MAC result and OV is the two’s complement overflow. Note that MAC AB

will not clear OV if it was previously set to one.

Three additional extended instructions operate directly on the M register. CLR M (A5 E4H)

clears the entire 40-bit register in two clock cycles. LSL M (A5 23H) and ASR (A5 03H) shift M

one bit to the left and right respectively. Right shifts are done arithmetically, i.e. the sign is

preserved.

The 40-bit M register is accessible 16-bits at a time through a sliding window as shown in Figure

5-4. The MRW

1-0 bits in DSPR (Table 5-1) select which 16-bit segment is currently accessible

through the MACL and MACH addresses. For normal fixed point operations the window can be

fixed to the rank of interest. For example, multiplying two 1.15 format numbers places a 2.30 for-

mat result in the M register. If MRW is set to 10B, a 1.15 value is obtained after performing a

single LSL M.

MAC AB:

AX ACC

}

BX B

{, }

←

ACC

16 x 16-bit Signed MULT

40-bit ADD

Shifter

MACH

MACL

PSW

MRW

SMLA

SMLB

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