AT89LP51RB2 datasheet(59/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Interrupts

The AT89LP51RB2/RC2/IC2 provides 11 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (Timers 0, 1 and 2), a serial port interrupt, an SPI interrupt, a key-

board interrupt, a PCA interrupt, an analog comparator interrupt and an ADC interrupt. These

interrupts and the system reset each have a separate program vector at the start of the program

memory space.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the

interrupt enable registers: IEN0 and IEN1. The IEN0 register also contains a global disable bit,

EA, which disables all interrupts. All of the bits that generate interrupts can be set or cleared by

software, with the same result as though they had been set or cleared by hardware. That is,

interrupts can be generated and pending interrupts can be canceled in software.

9.1

Interrupt Priority

Each interrupt source can be individually programmed to one of four priority levels by setting or

clearing bits in the interrupt priority registers: IPL0, IPL1, IPH0 and IPH1. IPL0 and IPL1 hold the

low order priority bits and IPH0 and IPH1 hold the high priority bits for each interrupt as shown in

Table 9-2. An interrupt service routine in progress can be interrupted by a higher priority inter-

rupt, but not by another interrupt of the same or lower priority. The highest priority interrupt

cannot be interrupted by any other interrupt source. If two requests of different priority levels are

pending at the end of an instruction, the request of higher priority level is serviced. If requests of

the same priority level are pending at the end of an instruction, an internal polling sequence

determines which request is serviced. The polling sequence is based on the vector address; an

interrupt with a lower vector address has higher priority than an interrupt with a higher vector

address, except in the case of the PCA, whose polling priority is moved up by two as shown in

Table 9-1 and Figure 9-1. Note that the polling sequence is only used to resolve pending

requests of the same priority level.

Table 9-1.

Interrupt Vector Addresses and Priority

Polling

Priority

Interrupt

Source

Vector

Address

System Reset

RST or POR or BOD

0000H

External Interrupt 0

IE0

0003H

Timer 0 Overflow

TF0

000BH

External Interrupt 1

IE1

0013H

Timer 1 Overflow

TF1

001BH

Serial Port Interrupt

RI or TI

0023H

Timer 2 Interrupt

TF2 or EXF2

002BH

PCA Interrupt

CF, CCF0, CCF1, CCF2, CCF3 or CCF4

0033H

Keyboard Interrupt

KBF7-0

003BH

Two-Wire Interrupt

0043H

SPI Interrupt

SPIF or MODF or TXE

004BH

reserved

0053H

Analog Comparator Interrupt

CFA or CFB

005BH

ADC Interrupt

ADIF

0063H

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