AT89LP51RB2 datasheet(39/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

5.4.2.3

Circular Buffers

The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in

circular buffer mode. The AT89LP51RB2/RC2/IC2 maps circular buffers into two identically

sized regions of EDATA/XDATA. These buffers can speed up convolution computations such as

FIR and IAR digital filters. The length of the buffers are set by the value of the FIRD (E3H) regis-

ter for up to 256 entries. Buffer A is mapped from 0000H to FIRD and Buffer B is mapped from

0100H to 100H+FIRD as shown in Figure 5-5. Both data pointers may operate in either buffer.

When circular buffer mode is enabled, updates to a data pointer referencing the buffer region will

follow circular addressing rules. If the data pointer is equal to FIRD or 100H+FIRD any incre-

ment will cause it to overflow to 0000H or 0100H respectively. If the data pointer is equal to

0000H or 0100H any decrement will cause it to underflow to FIRD or 100H+FIRD respectively.

In this mode, updates can be either an explicit INC DPTR or an automatic update using DPUn

where the DPDn bits control the direction. The data pointer will increment or decrement normally

at any other addresses. Therefore, when circular addressing is in use, the data pointers can still

operate as regular pointers in the FIRD+1 to 00FFH and greater than 100H+FIRD ranges.

Figure 5-5.

Circular Buffer Mode

5.5

Instruction Set Extensions

Table 5-10 lists the additions to the 8051 instruction set that are supported by the

AT89LP51RB2/RC2/IC2. For more information on the instruction set see Section 22. “Instruction

Set Summary” on page 173. For detailed descriptions of the extended instructions see Section

22.1 “Instruction Set Extensions” on page 177.

0000h

DPTR

0100h

FIRD

100h + FIRD

DPTR

Table 5-10.

AT89LP51RB2/RC2/IC2 Extended Instructions

Opcode

Mnemonic

Description

Bytes

Cycles

A5 00

BREAK

Software breakpoint

A5 03

ASR M

Arithmetic shift right of M register

A5 23

LSL M

Logical shift left of M register

A5 73

JMP @A+PC

Indirect jump relative to PC

A5 90

MOV /DPTR, #data16

Move 16-bit constant to alternate data

pointer

A5 93

MOVC A, @A+/DPTR

Move code location to ACC relative to

alternate data pointer

A5 A3

INC /DPTR

Increment alternate data pointer

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