AT89LP51RB2 datasheet(18/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

3.3.2

External Data Memory Interface

The AT89LP51RB2/RC2/IC2 uses the standard 8051 external data memory interface with the

upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE,

RD and WR strobes. The interface may be used in two different configurations depending on

which type of MOVX instruction is used to access XDATA.

Figure 3-7 shows a hardware configuration for accessing up to 64K bytes of external RAM using

a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the RAM. The

Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-

ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte

throughout the operation. The MOVX @DPTR instructions use Linear Address mode.

Figure 3-7.

External Data Memory 16-bit Linear Address Mode

Figure 3-8 shows a hardware configuration for accessing 256-byte blocks of external RAM using

an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE

strobe is used to latch the address byte into an external register so that Port 0 can be freed for

data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the mem-

ory; however, this operation is not handled automatically by hardware. The software application

must change the Port 2 register when appropriate to access different pages. The MOVX @Ri

instructions use Paged Address mode.

Figure 3-8.

External Data Memory 8-bit Paged Address Mode

Note that prior to using the external memory interface, WR (P3.6) and RD (P3.7) must be config-

ured as outputs. See Section 12.1 “Port Configuration” on page 69. P0 and P2 are configured

automatically to push-pull output mode when outputting address or data and P0 is automatically

tristated when inputting data regardless of the port configuration. The Port 0 configuration will

determine the idle state of Port 0 when not accessing the external memory.

ALE

AT89LP

DATA

LATCH

EXTERNAL

DATA

MEMORY

ADDR

I/O

ALE

AT89LP

DATA

LATCH

EXTERNAL

DATA

MEMORY

ADDR

PAGE

BITS

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