AT89LP51RB2 datasheet(52/254 Pages) ATMEL

52 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 7-2.

Power-on Reset Sequence

Note:

tPOR is approximately 143 µs ± 5%.

7.2

Brown-out Reset

The AT89LP51RB2/RC2/IC2 has an on-chip Brown-out Detection (BOD) circuit for monitoring

the V

DD level during operation by comparing it to a fixed trigger level. The trigger level VBOD for

the BOD is nominally 2.0V. The purpose of the BOD is to ensure that if V

DD fails or dips while

executing at speed, the system will gracefully enter reset without the possibility of errors induced

by incorrect execution. A BOD sequence is shown in Figure 7-3. When V

DD decreases to a value

below the trigger level V

BOD, the internal reset is immediately activated. When VDD increases

above the trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal

reset after the specified time-out period has expired (Table 7-1).

The BOD does not generate a reset output pulse except as part of a POR event.

Table 7-1.

Start-up Timer Settings

SUT Fuse 1

SUT Fuse 0

Clock Source

SUT (± 5%) µs

Internal RC/External Clock

Crystal Oscillator

1024

Internal RC/External Clock

512

Crystal Oscillator

2048

Internal RC/External Clock

1024

Crystal Oscillator

4096

Internal RC/External Clock

4096

Crystal Oscillator

16384

VDD

RST

Time-out

POR

RHD

POR

Internal

Reset

RST

Internal

Reset

SUT

BOD

(RST left unconnected)

(RST extended

externally)

POL

(POL Tied to VCC)

output

input

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