AT89LP51RB2 datasheet(66/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

10. External Interrupts

The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP51RB2/RC2/IC2 may be used as external

interrupt sources. The external interrupts can be programmed to be level-activated or transition-

activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is

triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In

this mode if successive samples of the INTx pin show a high in one cycle and a low in the next

cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each clock cycle, an input high or low should

hold for at least 2 system periods to ensure sampling. If the external interrupt is transition-acti-

vated, the external source has to hold the request pin high for at least two clock cycles, and then

hold it low for at least two clock cycles to ensure that the transition is seen so that interrupt

request flag IEx will be set. IEx will be automatically cleared by the CPU when the service rou-

tine is called if generated in edge-triggered mode. If the external interrupt is level-activated, the

external source has to hold the request active until the requested interrupt is actually generated.

Then the external source must deactivate the request before the interrupt service routine is com-

pleted, or else another interrupt will be generated. Both INT0 and INT1 may wake up the device

from the Power-down state.

Other peripheral pins can also generate interrupts in response to an external event:

• A negative edge on the T2EX pin (P1.1) can set the EXF2 flag in T2CON

•Transitions on the PCA capture inputs CEX0–CEX4 (P1.3–7) can set the CCFx bits in CCON

•Transitions or levels on Port 1 can set the bits in KBF using the keyboard interface (see next

section).

11. Keyboard Interface and General-purpose Interrupts

The AT89LP51RB2/RC2/IC2 implements a keyboard interface allowing the connection of a 1xn

to 8 x n matrix keyboard. The keyboard function provides 8 configurable external interrupts on

Port 1. Each port pin can detect high/low levels or positive/negative edges. The keyboard inputs

are considered as 8 independent interrupt sources sharing the same interrupt vector. The KBE

registers determine the mode for each individual pin. KBMOD selects between level-sensitive

and edge-triggered mode. KBLS selects between high/low in level mode and positive/negative in

edge mode. A block diagram is shown in Figure 11-1.

The pins of Port 1 are sampled every clock cycle. In level-sensitive mode, a valid level must

appear in two successive samples before generating the interrupt. In edge-triggered mode, a

transition will be detected if the value changes from one sample to the next. When an interrupt

condition on a pin is detected, and that pin is enabled, the appropriate flag in the KBF register is

set. The flags in KBF must be cleared by software. Any enabled keyboard interrupt may wake up

the device from the Idle or Power-down state.

Unlike AT89C51RB2/RC2/IC2 the flags in KBF are not cleared by reading the register. The soft-

ware may clear each bit individually or all at once. This allows the interface to be used for

general purpose external interrupts where some flags can be left pending between calls to the

service routine. Each flag can also be made pending by software by writing a one to it. To

achieve the same behavior as AT89C51RB2/RC2/IC2, the service routine must clear the entire

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