MPC8569E datasheet(106/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Enhanced Local Bus Controller

Freescale Semiconductor

106

The following table describes the timing specifications of the enhanced local bus interface at BVDD = 3.3, 2.5, and 1.8 V DC

with PLL disabled.

Table 67. Enhanced Local Bus Timing Specifications (BVDD = 3.3 V, 2.5 V, and 1.8 V)—PLL Bypassed

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Max

Unit

Notes

Enhanced local bus cycle time

tLBK

—

Enhanced local bus duty cycle

tLBKH/tLBK

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—150

Input setup

(except LUPWAIT/LFRB)

tLBIVKH

6.5

—

Input hold

(except LUPWAIT/LFRB)

tLBIXKH

1—

—

Input setup

(for LUPWAIT/LFRB)

tLBIVKL

6.5

—

Input hold

(for LUPWAIT/LFRB)

tLBIXKL

1—

—

Output delay

(Except LALE)

tLBKLOV

—1.5

—

Output hold

(Except LALE)

tLBKLOX

–3.5

—

Enhanced local bus clock to output high

impedance for LAD/LDP

tLBKLOZ

—2

LALE output negation to LAD/LDP output

transition (LATCH hold time)

tLBONOT

1 – 1 ns

(LBCR[AHD] = 0)

1/2 – 1 ns

(LBCR[AHD] = 1)

—

eLBC

controller

clock

cycle

(=1

platform

clock

cycle in

ns)

Notes:

1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.

2. Skew measured between different LCLK signals at BVDD/2.

3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined

by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not

the external LCLK. LCLK cycle = eLBC controller clock cycle

× LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to

0 and eLBC runs at maximum hold time.

5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.

6. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

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