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910GL датащи(PDF) 249 Page - Intel Corporation |
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910GL датащи(HTML) 249 Page - Intel Corporation |
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249 / 426 page ![]() Functional Description R Datasheet 249 12.7.1 Analog Display Port Characteristics The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector. Display devices (such as LCD panels) with analog inputs may work satisfactory but no functionality has been added to the signals to enhance that capability. Table 12-7. Analog Port Characteristics Signal Port Characteristic Support Voltage Range 0.7 V p-p only Monitor Sense Analog Compare Analog Copy Protection No RGB Sync on Green No Voltage 2.5 V Enable/Disable Port control Polarity adjust VGA or port control Composite Sync Support No Special Flat Panel Sync No HSYNC VSYNC Stereo Sync No Voltage Externally buffered to 5V DDC Control Through GPIO interface 12.7.1.1 Integrated RAMDAC The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the CRT monitor. The GMCH’s integrated 400 MHz RAMDAC supports resolutions up to 2048 x 1536 @ 85Hz. Three 8-bit DACs provide the RED, GREEN, and BLUE signals to the monitor. 12.7.1.2 Sync Signals HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since these levels cannot be generated internal to the device, external level shifting buffers are required. These signals can be polarity adjusted and individually disabled in one of the two possible states. The sync signals power up disabled in the high state. No composite sync or special flat panel sync support is included. 12.7.1.3 VESA/VGA Mode VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the VGA CRTC registers. Timings are generated based on the VGA register values and the timing generator registers are not used. |
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