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910GL датащи(PDF) 51 Page - Intel Corporation |
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910GL датащи(HTML) 51 Page - Intel Corporation |
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51 / 426 page ![]() Signal Description R Datasheet 51 Table 2-6. Clocking Reset and S3 States Interface Signal Name I/O State During RSTIN# Assertion State After RSTIN# De- assertion S3 Pull-up/ Pull-down HCLKN I IN IN IN HCLKP I IN IN IN GCLKN I IN IN IN GCLKP I IN IN IN DREFCLKN I IN IN IN Clocks DREFCLKP I IN IN IN Table 2-7. MISC Reset and S3 States Interface Signal Name I/O State During RSTIN# Assertion State After RSTIN# De-assertion S3 Pull-up/ Pull-down RSTIN# I IN IN IN PWROK I HV HV HV EXTTS# I PU PU PU BSEL[2:0] I TRI TRI TRI MTYPE I TERM HV TERM HV TERM HV EXP_SLR I TERM HV TERM HV TERM HV ICH_SYNC# O PU PU PU SDVO_CTRLCLK O TRI TRI TRI Misc. SDVO_CTRLDATA I/O TERM PD TRI TERM PD Table 2-8. DAC Reset and S3 States (Intel ® 82915G/82915GV/82915GL/82910GL GMCH only) Interface Signal Name I/O State During RSTIN# Assertion State After RSTIN# Deassertion S3 Pull-up/ Pull-down HSYNC O LV LV VSYNC O LV LV RED O TRI TRI TRI RED# O TRI TRI TRI GREEN O TRI TRI TRI GREEN# O TRI TRI TRI BLUE O TRI TRI TRI BLUE# O TRI TRI TRI REFSET O TRI 0.5* VCCA_DAC TRI 255 Ω 1% Resistor to Ground DDC_CLK I/O IN IN IN DAC DDC_DATA I/O IN IN IN § |
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