910GL datasheet(65/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

Host Bridge/DRAM Controller

Registers (D0:F0)

The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).

Warning: Address locations that are not listed are considered Reserved registers locations. Reads to

Reserved registers may return non-zero values. Writes to reserved locations may cause system

failures.

All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in

this component are not included in this document. The reserved/unimplemented space in the PCI

configuration header space is not documented as such in this summary.

Table 4-1. Device 0 Function 0 Register Address Map Summary

Address

Offset

Symbol

Default

Value

Access

00–01h

VID

Vendor Identification

8086h

02–03h

DID

Device Identification

2580h

04–05h

PCICMD

PCI Command

0006h

RO, R/W

06–07h

PCISTS

PCI Status

0090h

RO,

R/W/C

08h

RID

Revision Identification

See register

description

09–0Bh

Class Code

060000h

0Ch

—

Reserved

—

0Dh

MLT

Master Latency Timer

00h

0Eh

HDR

Header Type

00h

0F–2Bh

—

Reserved

—

2C–2Dh

SVID

Subsystem Vendor Identification

0000h

R/W/O

2E–2Fh

SID

Subsystem Identification

0000h

R/W/O

30–33h

—

Reserved

—

34h

CAPPTR

Capabilities Pointer

EOh

35–3Fh

—

Reserved

—

40–43h

EPBAR

Egress Port Base Address

00000000h

44–47h

MCHBAR

GMCH Memory Mapped Register Range

Base Address

00000000h

R/W

48–4Bh

PCIEXBAR

PCI Express* Register Range Base Address

E0000000h

R/W

4C–4Fh

DMIBAR

Root Complex Register Range Base

Address

00000000h

R/W

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