910GL datasheet(70/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.4

PCISTS—PCI Status (D0:F0)

PCI Device:

Address Offset:

06h

Default Value:

0090h

Access:

RO, R/W/C

Size:

16 bits

This status register reports the occurrence of error events on Device 0’s PCI interface. Since the

(G)MCH Device 0 does not physically reside on Primary PCI, many of the bits are not

implemented.

Bit

Access &

Default

Description

Detected Parity Error (DPE): Hardwired to a 0.

R/W/C

Signaled System Error (SSE): Software clears this bit by writing a 1 to it.

1 = The (G)MCH Device 0 generated an SERR message over DMI for any

enabled Device 0 error condition. Device 0 error conditions are enabled in the

PCICMD, and ERRCMD registers. Device 0 error flags are read/reset from

the PCISTS, or ERRSTS registers.

R/WC

Received Master Abort Status (RMAS): Software clears this bit by writing a 1 to

it.

1 = (G)MCH generated a DMI request that receives an Unsupported Request

completion packet.

R/WC

Received Target Abort Status (RTAS): Software clears this bit by writing a 1 to

it.

1 = (G)MCH generated a DMI request that receives a Completer Abort

completion packet.

Signaled Target Abort Status (STAS): The (G)MCH will not generate a Target

Abort DMI completion packet or Special Cycle. This bit is not implemented in the

(G)MCH and is hardwired to a 0.

10:9

00b

DEVSEL Timing (DEVT): These bits are hardwired to "00". Device 0 does not

physically connect to Primary PCI. These bits are set to "00" (fast decode) so

that optimum DEVSEL timing for Primary PCI is not limited by the (G)MCH.

Master Data Parity Error Detected (DPD): PERR signaling and messaging are

not implemented by the (G)MCH; therefore, this bit is hardwired to 0.

Fast Back-to-Back (FB2B): Hardwired to 1. Device 0 does not physically

connect to Primary PCI. This bit is set to 1 (indicating fast back-to-back

capability) so that the optimum setting for Primary PCI is not limited by the

(G)MCH.

Reserved

66 MHz Capable: Does not apply to PCI Express*. Hardwired to 0.

Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration

software that this device/function implements a list of new capabilities. A list of

new capabilities is accessed via register CAPPTR at configuration address offset

34h. Register CAPPTR contains an offset pointing to the start address within

configuration space of this device where the Capability standard register resides.

3:0

Reserved

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