910GL datasheet(71/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.5

RID—Revision Identification (D0:F0)

PCI Device:

Address Offset:

08h

Default Value:

See bit description

Access:

Size:

8 bits

This register contains the revision number of the (G)MCH Device 0.

Bit

Access &

Default

Description

7:0

00h

Revision Identification Number (RID): This field indicates the number of times

that this device in this component has been “stepped” through the manufacturing

process. Refer to the Intel

® 82915G/82915P/82915GV/82910GL Express Chipset

Specification Update for the value of the Revision ID Register.

4.1.6

CC—Class Code (D0:F0)

PCI Device:

Address Offset:

09h

Default Value:

060000h

Access:

Size:

24 bits

This register identifies the basic function of the device, a more specific sub-class, and a register-

specific programming interface.

Bit

Access &

Default

Description

23:16

06h

Base Class Code (BCC): This is an 8-bit value that indicates the base class

code for the (G)MCH.

06h = Bridge device.

15:8

00h

Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of

Bridge into which the (G)MCH falls.

00h = Host Bridge.

7:0

00h

Programming Interface (PI): This is an 8-bit value that indicates the

programming interface of this device. This value does not specify a particular

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