910GL datasheet(11/426 Pages) INTEL

11 / 426 page

Datasheet

15.2

XOR Test Mode Initialization for DDR................................................................ 400

15.3

XOR Test Mode Initialization for DDR2.............................................................. 400

15.4

XOR Chain Definition ......................................................................................... 401

15.5

DDR XOR Chains............................................................................................... 401

15.6

DDR2 XOR Chains............................................................................................. 414

15.7

PADs Excluded from XOR Mode(s) ................................................................... 426

Figures

Figure 1-1. Intel

® 915G Express Chipset System Block Diagram Example ..................... 18

Figure 1-2. Intel

® 915P Express Chipset System Block Diagram Example ..................... 19

Figure 1-3. Intel

® 915GV Express Chipset System Block Diagram Example................... 20

Figure 1-4. Intel

® 910GL Express Chipset System Block Diagram Example ................... 21

Figure 1-5. Intel

® 915PL Express Chipset System Block Diagram Example ................... 22

Figure 1-6. Intel

® 915GL Express Chipset System Block Diagram Example ................... 23

Figure 2-1. Intel

® (G)MCH Signal Interface Diagram........................................................ 34

Figure 3-1. Conceptual Chipset PCI Configuration Diagram............................................ 55

Figure 3-2. Register Organization (Representative of the Intel

® 82915G GMCH) ........... 57

Figure 3-3. DMI Type 0 Configuration Address Translation ............................................. 59

Figure 3-4. DMI Type 1 Configuration Address Translation ............................................. 59

Figure 3-5. Memory Map to PCI Express* Device Configuration Space .......................... 60

Figure 3-6. Intel

® 915x GMCH Configuration Cycle Flowchart......................................... 62

Figure 6-1. Link Declaration Topology ............................................................................ 109

Figure 11-1. System Address Ranges ............................................................................ 207

Figure 11-2. Microsoft MS-DOS* Legacy Address Range ............................................. 208

Figure 11-3. Main Memory Address Range.................................................................... 211

Figure 11-4. PCI Memory Address Range...................................................................... 213

Figure 12-1. System Memory Styles............................................................................... 225

Figure 12-2. Integrated Graphics Device Block Diagram ............................................... 235

Figure 12-3. System Clocking Example.......................................................................... 254

Figure 14-1. Intel

® 82915G GMCH Ballout for DDR2 (Top View: Columns 1–12) ......... 268

Figure 14-2. Intel

® 82915G GMCH Ballout for DDR2 (Top View: Columns 13–24) ....... 269

Figure 14-3. Intel

® 82915G GMCH Ballout for DDR2 (Top View: Columns 25–35) ....... 270

Figure 14-4. Intel

® 82915G GMCH Ballout for DDR (Top View: Columns 1–12 ) .......... 330

Figure 14-5. Intel

® 82915G GMCH Ballout for DDR (Top View: Columns 13–24 ) ........ 331

Figure 14-6. Intel

® 82915G GMCH Ballout for DDR (Top View: Columns 25–35 ) ........ 332

Figure 14-7. (G)MCH Package Dimensions ................................................................... 396

Figure 14-8. (G)MCH Component Keep-Out Restrictions .............................................. 397

Figure 15-1. XOR Test Mode Initialization Cycles .......................................................... 400

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