910GL datasheet(94/426 Pages) INTEL

номер детали	910GL

подробное описание детали	Express Chipset

PDF	426 Pages

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производитель	INTEL [Intel Corporation]

домашняя страница	http://www.intel.com

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.31

SKPD—Scratchpad Data (D0:F0)

PCI Device:

Address Offset:

DCh

Default Value:

00000000h

Access:

R/W

Size:

32 bits

This register holds 32 writable bits with no functionality behind them. It is for the convenience of

BIOS and graphics drivers.

Bit

Access &

Default

Description

31:0

R/W

00000000 h

Scratchpad Data: 1 DWord of data storage.

4.1.32

CAPID0—Capability Identifier (D0:F0)

PCI Device:

Address Offset:

E0h

Default Value:

000000000001090009h

Access:

Size:

72 bits

Bit

Access &

Default

Description

71:28

Reserved

27:24

CAPID Version: This field has the value 0001b to identify the first revision of the

CAPID register definition.

23:16

09h

CAPID Length: This field has the value 09h to indicate the structure length

(9 bytes).

15:8

00h

Next Capability Pointer: This field is hardwired to 00h indicating the end of the

capabilities linked list.

7:0

09h

CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the

PCI SIG for vendor dependent capability pointers.

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