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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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910GL датащи(PDF) 80 Page - Intel Corporation |
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910GL датащи(HTML) 80 Page - Intel Corporation |
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80 / 426 page  Host Bridge/DRAM Controller Registers (D0:F0) R 80 Datasheet Bit Access & Default Description 4 R/W 1b 82915G/82915GV/82915GL/82910GL GMCH: Internal Graphics Engine Function 1 (D2F1EN): 0 = Bus 0 Device 2 Function 1 is disabled and hidden 1 = Bus 0 Device 2 Function 1 is enabled and visible Note: Setting this bit to enabled when bit 3 is 0 has no meaning. 82915P/82915PL MCH: Reserved. 3 R/W 1b 82915G/82915GV/82915GL/82910GL GMCH: Internal Graphics Engine Function 0 (D2F0EN): 0 = Bus 0 Device 2 Function 0 is disabled and hidden 1 = Bus 0 Device 2 Function 0 is enabled and visible 82915P/82915PL MCH: Reserved. 2 Reserved 1 R/W 1b Strap dependent 82915G/82915P/82915PL (G)MCH: PCI Express* Port (D1EN): 0 = Bus 0 Device 1 Function 0 is disabled and hidden. This also gates PCI Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb). 1 = Bus 0 Device 1 Function 0 is enabled and visible. The SDVO Presence hardware strap determines default value. Device 1 is disabled on Reset when the SDVO Presence strap (SDVO_CTLRDATA signal) is sampled high, and is enabled otherwise. 82915GV/82915GL/82910GL GMCH: Reserved. 0 RO 1b Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore hardwired to 1. |
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