910GL datasheet(50/426 Pages) INTEL

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Signal Description

Datasheet

Interface

Signal Name

I/O

State During

RSTIN#

Assertion

State After RSTIN#

De-assertion

Pull-up/

Pull-down

SWE_B#

TRI

SDQ_B[63:0]

I/O

TRI

System

Memory

(DDR)

SDM_B[7:0]

TRI

SDQS_B[7:0]

I/O

TRI

SDQS_B[7:0]#

I/O

TRI

SCKE_B[3:0]

SRCOMP0

I/O

TRI

TRI (after RCOMP)

TRI

SRCOMP1

I/O

TRI

TRI (after RCOMP)

TRI

SM_SLEWIN[1:0]

SM_SLEWOU[1:0]

TRI

TRI (after RCOMP)

TRI

SMVREF[1:0]

SOCOMP[1:0]

I/O

TRI

DDR2: 40

Ω

resistor to

ground

Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States

Interface

Signal Name

I/O

State During

RSTIN#

Assertion

State After RSTIN#

De-assertion

Pull-up/

Pull-down

EXP_RXN[15:0]

I/O

CMCT

EXP_RXP[15:0]

I/O

CMCT

EXP_TXN[15:0]

CMCT 1.0 V

EXP_TXP[15:0]

CMCT 1.0 V

EXP_COMPO

TRI

TRI (after RCOMP)

TRI

PCI

Express*-

Graphics

EXP_COMPI

TRI

TRI (after RCOMP)

TRI

Table 2-5. DMI Reset and S3 States

Interface

Signal Name

I/O

State During

RSTIN#

Assertion

State After RSTIN#

De-assertion

Pull-up/ Pull-

down

DMI_RXN[3:0]

I/O

CMCT

DMI_RXP[3:0]

I/O

CMCT

DMI_TXN[3:0]

CMCT 1.0 V

DMI

DMI_TXP[3:0]

CMCT 1.0 V

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