910GL datasheet(60/426 Pages) INTEL

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3.3.4

PCI Express* Enhanced Configuration Mechanism

PCI Express extends the configuration space to 4096 bytes per device/function as compared to

256 bytes allowed by PCI Specification, Revision 2.3. PCI Express configuration space is divided

into a PCI 2.3 compatible region that consists of the first 256B of a logical device’s configuration

space and a PCI Express extended region that consists of the remaining configuration space.

The PCI compatible region can be accessed using either the mechanism defined in the previous

section or using the enhanced PCI Express configuration access mechanism described in this

section. The extended configuration registers may only be accessed using the enhanced PCI

Express configuration access mechanism. To maintain compatibility with PCI configuration

addressing mechanisms, system software must access the extended configuration space using

32-bit operations (32-bit aligned) only. These 32-bit operations include byte enables allowing

only appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express

memory mapped configuration address space are not supported. All changes made using either

access mechanism are equivalent. The enhanced PCI Express configuration access mechanism

uses a flat memory-mapped address space to access device configuration registers. This address

space is reported by the system firmware to the operating system. The PCIEXBAR register

defines the base address for the 256-MB block of addresses below top of addressable memory

(currently 4 GB) for the configuration space associated with all devices and functions that are

potentially a part of the PCI Express root complex hierarchy. The PCI Express Configuration

Transaction Header includes an additional 4 bits (Extended Register Address[3:0]) between the

Function Number and Register Address fields to provide indexing into the 4 KB of configuration

space allocated to each potential device. For PCI Compatible Configuration Requests, the

Extended Register Address field must be all zeros.

Figure 3-5. Memory Map to PCI Express* Device Configuration Space

MemMap_PCIExpress

Bus 255

0xFFFFFFFh

Bus 1

Bus 0

0x1FFFFFh

0xFFFFFh

Device 31

0xFFFFFh

Device 1

Device 0

0xFFFFh

0x7FFFh

Function 7

0xFFFFFh

Function 1

Function 0

0xFFFFh

0x7FFFh

0xFFFh

PCI

Compatible

Config Space

PCI

Compatible

Config Header

0xFFh

0x3Fh

PCI Express

Extended

Configuration

Space

Located By PCI

Express Base

Address

Just the same as with PCI devices, each device is selected based on decoded address information

that is provided as a part of the address portion of Configuration Request packets. A PCI Express

device will decode all address information fields (bus, device, function, and extended address

numbers) to provide access to the correct register.

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