910GL datasheet(86/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.23

PAM5—Programmable Attribute Map 5 (D0:F0)

PCI Device:

Address Offset:

95h

Default Value:

00h

Access:

R/W

Size:

8 bits

This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h-

0E7FFFh.

Bit

Access &

Default

Description

7:6

Reserved

5:4

R/W

00b

0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the steering of read

and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.

00 = DRAM Disabled: Accesses are directed to the DMI.

01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the

DMI.

10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.

3:2

Reserved

1:0

R/W

00b

0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the steering of read

and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.

00 = DRAM Disabled: Accesses are directed to the DMI.

01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the

DMI.

10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.

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