910GL datasheet(26/426 Pages) INTEL

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Introduction

Datasheet

1.2

Reference Documents

Document Title

Document

Number/Location

Intel

® 915G/915GV/910GL Express Chipset Thermal Design Guide

http://intel.com/design/chip

sets/designex/301469.htm

Intel

® I/O Controller Hub 6 (ICH6) Family Datasheet

http://developer.intel.com/d

esign/chipsets/datashts/30

1473.htm

Advanced Configuration and Power Interface Specification, Version 2.0

http://www.acpi.info/

Advanced Configuration and Power Interface Specification, Version 1.0b

http://www.acpi.info/

The PCI Local Bus Specification, Version 2.3

http://www.pcisig.com/spe

cifications

PCI Express* Specification, Version 1.0a

http://www.pcisig.com/spe

cifications

1.3

GMCH (MCH) Overview

The (G)MCH connects to the processor as shown in Figure 1-1, Figure 1-2, Figure 1-3, Figure

1-4, Figure 1-5, and Figure 1-6. A major role of the (G)MCH in a system is to manage the flow of

information between its interfaces: the processor interface (FSB), the System Memory interface

(DRAM controller), the Integrated Graphics interface (82915G/82915GV/82915GL/82910GL

GMCH only), the External Graphics interface via PCI Express (82915G/82915P/82915PL MCH

only), and the I/O Controller Hub through the DMI interface. This includes arbitrating between

the interfaces when each initiates transactions.

The (G)MCH supports one or two channels of DDR

(82915G/82915GV/82915GL/82915P/82915PL/82910GL) or DDR2 (82915G/82915GV/82915P)

SDRAM. The (G)MCH also supports the new PCI Express based external graphics attach. Thus,

the 915G/915GV/915GL/910GL/915P and 915PL Express chipsets are NOT compatible with

AGP (1X, 2X, 4X, or 8X).

To increase system performance, the (G)MCH incorporates several queues and a write cache. The

(G)MCH also contains advanced desktop power management logic.

1.3.1

Host Interface

The (G)MCH is optimized for both the Pentium 4 processors in the LGA775 socket and the

Celeron D processor in the FC-mPGA4 socket. The (G)MCH can use a single LGA 775 socket

processor. The (G)MCH supports FSB frequency of 533/800 MT/s (133/200 MHz HCLK) using

a scalable FSB Vcc_CPU (82910GL only supports 533 MT/s, 133 MHz HCLK). The (G)MCH

supports the Pentium 4 processor subset of the Extended Mode Scaleable Bus Protocol. The

primary enhancements over the Compatible Mode P6 bus protocol are: Source synchronous

double-pumped (2) Address and Source synchronous quad-pumped (4x) Data.

The (G)MCH supports 32-bit host addressing, decoding up to 4 GB of the processor’s memory

address space. Host-initiated I/O cycles are decoded to PCI Express, DMI, or the (G)MCH

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