910GL datasheet(224/426 Pages) INTEL

224 / 426 page

Functional Description

224

Datasheet

12.1.3

APIC Cluster Mode Support

This is required for backwards compatibility with existing software, including various operating

systems. As one example, beginning with Microsoft Windows 2000 there is a mode (boot.ini) that

allows an end user to enable the use of cluster addressing support of the APIC.

The (G)MCH supports three types of interrupt re-direction:

• Physical

• Flat-Logical

• Clustered-Logical

12.2

System Memory Controller

This section describes the (G)MCH system memory interface for both DDR memory and DDR2

memory. The (G)MCH supports both DDR and DDR2 memory and either one or two DIMMs per

channel.

Note:

The 82915G/82915GV GMCH and 82915P MCH support both DDR memory and DDR2

memory, and either one or two DIMMs per channel. The 82910GL only supports DDR memory

and a maximum of one DIMM per channel. The 82915PL and 82915GL support only DDR and

either one or two DIMMs per channel.

12.2.1

Memory Organization Modes

The system memory controller supports two styles of memory organization (Interleaved and

Asymmetric) and two modes of operation (DDR and DDR2). Rules for populating DIMM slots

are included in this chapter.

Interleaved Mode

This mode provides maximum performance on real applications. Addresses are ping-ponged

between the channels, and the switch happens after each cache line (64 byte boundary). If two

consecutive cache lines are requested, both may be retrieved simultaneously, since they are

guaranteed to be on opposite channels. The drawbacks of Interleaved Mode are that the system

designer must populate both channels of memory such that they have equal capacity, but the

technology and device width may vary from one channel to the other. Refer to Figure 12-1 for

further clarification.

Asymmetric Mode

This mode trades performance for system design flexibility. Unlike the previous mode, addresses

start in channel A and stay there until the end of the highest rank in channel A; then, addresses

continue from the bottom of channel B to the top. Real world applications are unlikely to make

requests that alternate between addresses that sit on opposite channels with this memory

organization, so in most cases, bandwidth will be limited to that of a single channel. The system

designer is free to populate or not to populate any rank on either channel, including either

degenerate single channel case. Refer to Figure 12-1 for further clarification.

910GL датащи(PDF) 224 Page - Intel Corporation

910GL датащи(HTML) 224 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL