910GL datasheet(220/426 Pages) INTEL

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System Address Map

220

Datasheet

11.4.9

I/O Address Space

The (G)MCH does not support the existence of any other I/O devices beside itself on the

processor bus. The (G)MCH generates either DMI or PCI Express bus cycles for all processor I/O

accesses that it does not claim. Within the host bridge, the (G)MCH contains two internal

registers in the processor I/O space. These locations are used to implement a configuration space

access mechanism.

The processor allows 64 KB+3 bytes to be addressed within the I/O space. The (G)MCH

propagates the processor I/O address without any translation on to the destination bus; therefore,

providing addressability for 64 KB+3 byte locations. Note that the upper 3 locations can be

accessed only during I/O address wrap-around when processor bus HA16# address signal is

asserted. HA16# is asserted on the processor bus when an I/O access is made to 4 bytes from

address 0FFFDh, 0FFFEh, or 0FFFFh. HA16# is also asserted when an I/O access is made to

2 bytes from address 0FFFFh.

For the 828915G GMCH, a set of I/O accesses (other than ones used for configuration space

access) are consumed by the internal graphics device if it is enabled. The mechanisms for internal

graphics I/O decode and the associated control are explained later.

The I/O accesses (other than ones used for configuration space access) are forwarded normally to

the DMI bus unless they fall within the PCI Express I/O address range as defined by the

mechanisms explained below. I/O writes are not posted. Memory writes to the ICH6 or PCI

Express are posted.

The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream

I/O cycles and configuration cycles should never occur. If one does occur, the request will route

as a read to memory address 0h so a completion is naturally generated (whether the original

request was a read or write). The transaction will complete with a UR completion status.

11.4.10

PCI Express* I/O Address Mapping (Intel

82915G/82915P/82915PL Only)

The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus

interface when processor-initiated I/O cycle addresses are within the PCI Express I/O address

range.

11.4.11

(G)MCH Decode Rules and Cross-Bridge Address Mapping

The following are (G)MCH decode rules and cross-bridge address mapping used in this chipset:

• VGAA = 000A_0000h – 000A_FFFFh

• MDA = 000B_0000h – 000B_7FFFh

• VGAB = 000B_8000h – 000B_FFFFh

• MAINMEM = 0100_0000 to TOLUD

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