910GL datasheet(143/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

Datasheet

143

Bit

Access &

Default

Description

R/W

ISA Enable (ISAEN): This bit is needed to exclude legacy resource decode to

route ISA resources to legacy decode path. This bit modifies the response by the

(G)MCH to an I/O access issued by the processor that target ISA I/O addresses.

This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT

registers.

0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O

transactions will be mapped to PCI Express Graphics.

1 = (G)MCH will not forward to PCI Express Graphics any I/O transactions

addressing the last 768 bytes in each 1-KB block, even if the addresses are

within the range defined by the IOBASE and IOLIMIT registers. Instead of

going to PCI Express Graphics, these cycles are forwarded to DMI where

they can be subtractively or positively claimed by the ISA bridge.

R/W

SERR Enable (SERREN)

0 = No forwarding of error messages from secondary side to primary side that

could result in an SERR.

1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR

message when individually enabled by the Root Control register.

Parity Error Response Enable (PEREN): This bit controls whether or not the

Master Data Parity Error bit in the Secondary Status register is set when the

MCH receives across the link (upstream) a Read Data Completion Poisoned

TLP.

0 = Master Data Parity Error bit in Secondary Status register cannot be set.

1 = Master Data Parity Error bit in Secondary Status register can be set..

910GL датащи(PDF) 143 Page - Intel Corporation