XIO2001 datasheet(28/131 Pages) TI

номер детали	XIO2001

подробное описание детали	Express??to PCI Bus Translation Bridge

PDF	131 Pages

Scroll/Zoom	100%

производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

Logo

28 / 131 page

Feature/Protocol Descriptions

PCI Express

Transmitter

PCI Express

Receiver

PCI Bus Interface

Configuration and

Memory Register

GPIO

Serial

EEPROM

Serial

IRQ

Reset

Controller

Clock

Generator

Power

Mgmt

3.1

Power-Up/-Down Sequencing

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

www.ti.com

This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified

block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the

PCI Express interface and the PCI bus interface is located at the bottom of the diagram.

Figure 3-1. XIO2001 Block Diagram

The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down

sequences describe how power is applied to these terminals.

In addition, the bridge has three resets: PERST, GRST and an internal power-on reset. These resets are

fully described in Section 3.2. The following power-up and power-down sequences describe how PERST

is applied to the bridge.

The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down

sequence and is included in the following power-up and power-down descriptions.

Feature/Protocol Descriptions

Submit Documentation Feedback

XIO2001 датащи(PDF) 28 Page - Texas Instruments