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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001 датащи(PDF) 4 Page - Texas Instruments |
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XIO2001 датащи(HTML) 4 Page - Texas Instruments |
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4 / 131 page  XIO2001 PCI Express™ to PCI Bus Translation Bridge SCPS212B – MAY 2009 – REVISED JULY 2009 www.ti.com 4.58 Serial-Bus Control and Status Register ................................................................................. 76 4.59 GPIO Control Register ..................................................................................................... 77 4.60 GPIO Data Register ........................................................................................................ 77 4.61 TL Control and Diagnostic Register 0 ................................................................................... 78 4.62 Control and Diagnostic Register 1 ....................................................................................... 79 4.63 Control and Diagnostic Register 2 ....................................................................................... 79 4.64 Subsystem Access Register .............................................................................................. 80 4.65 General Control Register .................................................................................................. 81 4.66 Clock Control Register ..................................................................................................... 83 4.67 Clock Mask Register ....................................................................................................... 84 4.68 Clock Run Status Register ................................................................................................ 85 4.69 Arbiter Control Register ................................................................................................... 86 4.70 Arbiter Request Mask Register ........................................................................................... 87 4.71 Arbiter Time-Out Status Register ........................................................................................ 88 4.72 Serial IRQ Mode Control Register ....................................................................................... 88 4.73 Serial IRQ Edge Control Register ........................................................................................ 89 4.74 Serial IRQ Status Register ................................................................................................ 91 4.75 Pre-Fetch Agent Request Limits Register .............................................................................. 92 4.76 Cache Timer Transfer Limit Register .................................................................................... 93 4.77 Cache Timer Lower Limit Register ....................................................................................... 94 4.78 Cache Timer Upper Limit Register ....................................................................................... 94 5 PCI Express Extended Configuration Space .......................................................................... 95 5.1 Advanced Error Reporting Capability ID Register ..................................................................... 95 5.2 Next Capability Offset/Capability Version Register .................................................................... 96 5.3 Uncorrectable Error Status Register ..................................................................................... 96 5.4 Uncorrectable Error Mask Register ...................................................................................... 97 5.5 Uncorrectable Error Severity Register ................................................................................... 98 5.6 Correctable Error Status Register ........................................................................................ 99 5.7 Correctable Error Mask Register ....................................................................................... 100 5.8 Advanced Error Capabilities and Control Register ................................................................... 101 5.9 Header Log Register ..................................................................................................... 101 5.10 Secondary Uncorrectable Error Status Register ...................................................................... 102 5.11 Secondary Uncorrectable Error Mask Register ....................................................................... 103 5.12 Secondary Uncorrectable Error Severity .............................................................................. 104 5.13 Secondary Error Capabilities and Control Register .................................................................. 105 5.14 Secondary Header Log Register ........................................................................................ 106 6 Memory-Mapped TI Proprietary Register Space .................................................................... 107 6.1 Device Control Map ID Register ........................................................................................ 107 6.2 Revision ID Register ...................................................................................................... 108 6.3 GPIO Control Register ................................................................................................... 108 6.4 GPIO Data Register ...................................................................................................... 109 6.5 Serial-Bus Data Register ................................................................................................ 110 6.6 Serial-Bus Word Address Register ..................................................................................... 110 6.7 Serial-Bus Slave Address Register .................................................................................... 110 6.8 Serial-Bus Control and Status Register ................................................................................ 111 6.9 Serial IRQ Mode Control Register ...................................................................................... 112 6.10 Serial IRQ Edge Control Register ...................................................................................... 112 6.11 Serial IRQ Status Register .............................................................................................. 114 6.12 Pre-Fetch Agent Request Limits Register ............................................................................. 116 6.13 Cache Timer Transfer Limit Register ................................................................................... 117 6.14 Cache Timer Lower Limit Register ..................................................................................... 117 6.15 Cache Timer Upper Limit Register ..................................................................................... 118 Contents 4 Submit Documentation Feedback |
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