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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001 датащи(PDF) 8 Page - Texas Instruments |
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XIO2001 датащи(HTML) 8 Page - Texas Instruments |
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8 / 131 page  XIO2001 PCI Express™ to PCI Bus Translation Bridge SCPS212B – MAY 2009 – REVISED JULY 2009 www.ti.com 4-20 PM Bridge Support Extension Register Description .......................................................................... 66 4-21 MSI Message Control Register Description ................................................................................... 67 4-22 MSI Message Lower Address Register Description .......................................................................... 68 4-23 MSI Message Data Register Description ...................................................................................... 68 4-24 PCI Express Capabilities Register Description ................................................................................ 69 4-25 Device Capabilities Register Description ...................................................................................... 70 4-26 Device Control Register Description ............................................................................................ 71 4-27 Device Status Register Description ............................................................................................. 72 4-28 Link Capabilities Register Description .......................................................................................... 73 4-29 Link Control Register Description ............................................................................................... 73 4-30 Link Status Register Description ................................................................................................ 74 4-31 Serial-Bus Slave Address Register Descriptions ............................................................................. 76 4-32 Serial-Bus Control and Status Register Description .......................................................................... 76 4-33 GPIO Control Register Description ............................................................................................. 77 4-34 GPIO Data Register Description ................................................................................................ 78 4-35 Control and Diagnostic Register 0 Description ............................................................................... 78 4-36 Control and Diagnostic Register 1 Description ............................................................................... 79 4-37 Control and Diagnostic Register 2 Description ............................................................................... 80 4-38 Subsystem Access Register Description ....................................................................................... 80 4-39 General Control Register Description .......................................................................................... 81 4-40 Clock Control Register Description ............................................................................................. 83 4-41 Clock Mask Register Description ............................................................................................... 84 4-42 Clock Run Status Register Description ........................................................................................ 85 4-43 Clock Control Register Description ............................................................................................. 86 4-44 Arbiter Request Mask Register Description ................................................................................... 87 4-45 Arbiter Time-Out Status Register Description ................................................................................. 88 4-46 Serial IRQ Mode Control Register Description ................................................................................ 89 4-47 Serial IRQ Edge Control Register Description ................................................................................ 89 4-48 Serial IRQ Status Register Description ........................................................................................ 91 4-49 Pre-Fetch Agent Request Limits Register Description ....................................................................... 92 4-50 Cache Timer Transfer Limit Register Description ............................................................................. 93 4-51 Cache Timer Lower Limit Register Description ............................................................................... 94 4-52 Cache Timer Upper Limit Register Description ............................................................................... 94 5-1 PCI Express Extended Configuration Register Map .......................................................................... 95 5-2 Uncorrectable Error Status Register Description ............................................................................. 96 5-3 Uncorrectable Error Mask Register Description ............................................................................... 97 5-4 Uncorrectable Error Severity Register Description ........................................................................... 98 5-5 Correctable Error Status Register Description ................................................................................ 99 5-6 Correctable Error Mask Register Description ................................................................................ 100 5-7 Advanced Error Capabilities and Control Register Description ............................................................ 101 5-8 Secondary Uncorrectable Error Status Register Description .............................................................. 102 List of Tables 8 Submit Documentation Feedback |
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