XIO2001 datasheet(49/131 Pages) TI

49 / 131 page

4.1

Vendor ID Register

4.2

Device ID Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

www.ti.com

SCPS212B – MAY 2009 – REVISED JULY 2009

Table 4-1. Classic PCI Configuration Register Map (continued)

OFFSET

Device Status 2

Device Control 2

098h

Link Capabilities 2

09Ch

Link Status 2

Link Control 2

0A0h

Slot Capabilities 2

0A4h

Slot Status 2

Slot Control 2

0A8h

Reserved

0ACh

Serial-bus control and

Serial-bus slave address(1)

Serial-bus word address(1)

Serial-bus data(1)

0B0h

status(1)

GPIO data(1)

GPIO control(1)

0B4h

Reserved

0B8h–0BCh

TL Control and diagnostic register 0(1)

0C0h

DLL Control and diagnostic register 1(1)

0C4h

PHY Control and diagnostic register 2(1)

0C8h

Reserved

0CCh

Subsystem access(1)

0D0h

General control(1)

0D4h

Reserved

Clock run status(1)

Clock mask

Clock control

0D8h

Reserved

Arbiter time-out status

Arbiter request mask(1)

Arbiter control(1)

0DCh

Serial IRQ edge control(1)

Reserved

Serial IRQ mode control(1)

0E0h

Reserved

Serial IRQ status

0E4h

Cache Timer Transfer Limit

PFA Request Limit

0E8h

Cache Timer Upper Limit

Cache Timer Lower Limit

0ECh

Reserved

0F0h–0FCh

This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas

Instruments.

PCI register offset:

00h

Read-only

Default value:

104Ch

BIT NUMBER

RESET STATE

This 16-bit read-only register contains the value 8231h, which is the device ID assigned by TI for the

bridge.

PCI register offset:

02h

Read-only

Default value:

8240h

BIT NUMBER

RESET STATE

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Classic PCI Configuration Space

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