XIO2001 datasheet(7/131 Pages) TI

7 / 131 page

XIO2001 PCI Express™ to PCI Bus Translation Bridge

www.ti.com

SCPS212B – MAY 2009 – REVISED JULY 2009

List of Tables

2-1

ZGU Terminals Sorted Alphanumerically

...................................................................................... 15

2-2

ZAJ Terminals Sorted Alphanumerically

....................................................................................... 17

2-3

XIO2001 Signal Names Sorted Alphabetically

................................................................................ 19

2-4

Power Supply Terminals

......................................................................................................... 21

2-5

Ground Terminals

................................................................................................................. 21

2-6

Combined Power Output Terminals

............................................................................................ 22

2-7

PCI Express Terminals

........................................................................................................... 22

2-8

PCI System Terminals

............................................................................................................ 23

2-9

JTAG Terminals

................................................................................................................... 25

2-10

Miscellaneous Terminals

......................................................................................................... 25

3-1

XIO2001 Reset Options

.......................................................................................................... 30

3-2

Initial Flow Control Credit Advertisements

..................................................................................... 32

3-3

Messages Supported by the Bridge

............................................................................................ 32

3-4

IRQ Interrupt to MSI Message Mapping

....................................................................................... 35

3-5

Classic PCI Arbiter Registers

.................................................................................................... 36

3-6

Type 0 Configuration Transaction

IDSEL Mapping

.................................................................................................................... 37

3-7

Interrupt Mapping In The Code Field

........................................................................................... 38

3-8

EEPROM Register Loading Map

................................................................................................ 43

3-9

Registers Used To Program Serial-Bus Devices

............................................................................. 45

3-10

Clocking In Low Power States

................................................................................................... 47

4-1

Classic PCI Configuration Register Map

....................................................................................... 48

4-2

Command Register Description

................................................................................................. 50

4-3

Status Register Description

...................................................................................................... 51

4-4

Class Code and Revision ID Register Description

........................................................................... 52

4-5

Device Control Base Address Register Description

.......................................................................... 54

4-6

I/O Base Register Description

................................................................................................... 55

4-7

I/O Limit Register Description

................................................................................................... 55

4-8

Secondary Status Register Description

........................................................................................ 56

4-9

Memory Base Register Description

............................................................................................. 57

4-10

Memory Limit Register Description

............................................................................................. 57

4-11

Prefetchable Memory Base Register Description

............................................................................. 58

4-12

Prefetchable Memory Limit Register Description

............................................................................. 58

4-13

Prefetchable Base Upper 32-Bit Register Description

....................................................................... 58

4-14

Prefetchable Limit Upper 32-Bit Register Description

........................................................................ 59

4-15

I/O Base Upper 16-Bit Register Description

................................................................................... 59

4-16

I/O Limit Upper 16-Bit Register Description

................................................................................... 60

4-17

Bridge Control Register Description

............................................................................................ 61

4-18

Power Management Capabilities Register Description

...................................................................... 65

4-19

Power Management Control/Status Register Description

................................................................... 65

List of Tables

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