XIO2001 datasheet(95/131 Pages) TI

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PCI Express Extended Configuration Space

5.1

Advanced Error Reporting Capability ID Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

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SCPS212B – MAY 2009 – REVISED JULY 2009

The programming model of the PCI Express extended configuration space is compliant to the PCI Express

Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCI

Express extended configuration map uses the PCI Express advanced error reporting capability.

All bits marked with a I are sticky bits and are reset by a global reset (GRST) or the internally-generated

power-on reset. All bits marked with a I are reset by a PCI Express reset (PERST), a GRST, or the

internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset,

PERST, GRST, or the internally-generated power-on reset.

Table 5-1. PCI Express Extended Configuration Register Map

OFFSET

Next capability offset / capability version

PCI Express advanced error reporting capabilities ID

100h

Uncorrectable error status register(1)

104h

Uncorrectable error mask register(1)

108h

Uncorrectable error severity register(1)

10Ch

Correctable error status register(1)

110h

Correctable error mask(1)

114h

Advanced error capabilities and control(1)

118h

Header log register(1)

11Ch

Header log register(1)

120h

Header log register(1)

124h

Header log register(1)

128h

Secondary uncorrectable error status(1)

12Ch

Secondary uncorrectable error mask(1)

130h

Secondary uncorrectable error severity register(1)

134h

Secondary error capabilities and control register(1)

138h

Secondary header log register(1)

13Ch

Secondary header log register(1)

140h

Secondary header log register(1)

144h

Secondary header log register(1)

148h

Reserved

14Ch–FFCh

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

This read-only register identifies the linked list item as the register for PCI Express advanced error

reporting capabilities. The register returns 0001h when read.

PCI Express extended register offset: 100h

Read-only

Default value:

0001h

BIT NUMBER

RESET STATE

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PCI Express Extended Configuration Space

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