XIO2001 datasheet(35/131 Pages) TI

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3.4.6

PCI Bus Clocks

XIO2001 PCI Express™ to PCI Bus Translation Bridge

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SCPS212B – MAY 2009 – REVISED JULY 2009

The bridge has a dedicated SERIRQ terminal for all PCI bus devices that support serialized interrupts.

This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always

generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame

through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never

generates an IRQ interrupt or MSI message.

The multiple message enable (MM_EN) field determines the number of unique MSI messages that are

sent upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable.

If fewer than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is

aliased. Table 3-4 illustrates the IRQ interrupt to MSI message mapping based on the number of enabling

messages.

Table 3-4. IRQ Interrupt to MSI Message Mapping

IRQ

1 MESSAGE

2 MESSAGES

4 MESSAGES

16 MESSAGES

8 MESSAGES ENABLED

INTERRUPT

ENABLED

IRQ0

MSI MSG #0

IRQ1

MSI MSG #0

MSI MSG #1

IRQ2

MSI MSG #0

MSI MSG #2

IRQ3

MSI MSG #0

MSI MSG #1

MSI MSG #3

IRQ4

MSI MSG #0

MSI MSG #4

IRQ5

MSI MSG #0

MSI MSG #1

MSI MSG #5

IRQ6

MSI MSG #0

MSI MSG #2

MSI MSG #6

IRQ7

MSI MSG #0

MSI MSG #1

MSI MSG #3

MSI MSG #7

IRQ8

MSI MSG #0

MSI MSG #8

IRQ9

MSI MSG #0

MSI MSG #1

MSI MSG #9

IRQ10

MSI MSG #0

MSI MSG #2

MSI MSG #10

IRQ11

MSI MSG #0

MSI MSG #1

MSI MSG #3

MSI MSG #11

IRQ12

MSI MSG #0

MSI MSG #4

MSI MSG #12

IRQ13

MSI MSG #0

MSI MSG #1

MSI MSG #5

MSI MSG #13

IRQ14

MSI MSG #0

MSI MSG #2

MSI MSG #6

MSI MSG #14

IRQ15

MSI MSG #0

MSI MSG #1

MSI MSG #3

MSI MSG #7

MSI MSG #15

The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit

memory write transactions. The system message and message number fields are included in bytes 0 and

1 of the data payload.

The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are

supported by the bridge.

Terminal PCLK66_SEL selects the default operating frequency. This signal works in conjunction with

terminal M66EN to determine the final output frequency. When PCLK66_SEL is asserted high then the

clock frequency will be either 66-MHz or 33-MHz depending on the state of M66EN. When M66EN is

asserted high then the clock frequency will be 66-MHz, when M66EN is de-asserted the clock frequency

will be 33-MHz. When PCLK66_SEL is de-asserted then the clock frequency will be either 50-MHz or

25-MHz. When M66EN is asserted high then the clock frequency will be 50-MHz, when M66EN is

de-asserted the clock frequency will be 25-MHz. The clock control register at offset D8h provides 7 control

bits to individually enable or disable each PCI bus clock output (see Section 4.66). The register default is

enabled for all 7 outputs.

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