XIO2001 datasheet(75/131 Pages) TI

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4.55 Serial-Bus Data Register

4.56 Serial-Bus Word Address Register

4.57 Serial-Bus Slave Address Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

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SCPS212B – MAY 2009 – REVISED JULY 2009

Table 4-30. Link Status Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

Link training. This bit has no function and is read-only 0b.

Retrain link. This bit has no function and is read-only 0b.

9:4

NLW

Negotiated link width. This field is read-only 00 0001b indicating the lane width is x1.

3:0

Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.

The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this

bus cycle. When reading data from the serial bus, this register contains the data read after bit 5

(REQBUSY) of the serial-bus control and status register (offset B3h, see Section 4.58) is cleared. This

PCI register offset:

B0h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

The value written to the serial-bus word address register represents the word address of the byte being

read from or written to the serial-bus device. The word address is loaded into this register prior to writing

the serial-bus slave address register (offset B2h, see Section 4.57) that initiates the bus cycle. This

PCI register offset:

B1h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

The serial-bus slave address register indicates the slave address of the device being targeted by the

serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register

initiates the cycle on the serial interface. See Table 4-31 for a complete description of the register

contents.

PCI register offset:

B2h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

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