XIO2001 datasheet(2/131 Pages) TI

2 / 131 page

Contents

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

www.ti.com

Introduction

....................................................................................................................... 11

1.1

Features

..................................................................................................................... 11

Overview

........................................................................................................................... 12

2.1

Description

.................................................................................................................. 12

2.2

Related Documents

........................................................................................................ 12

2.3

Documents Conventions

.................................................................................................. 13

2.4

Document History

.......................................................................................................... 13

2.5

Ordering Information

....................................................................................................... 13

2.6

Terminal Assignments

..................................................................................................... 13

2.7

Terminal Descriptions

...................................................................................................... 21

Feature/Protocol Descriptions

.............................................................................................. 28

3.1

Power-Up/-Down Sequencing

............................................................................................ 28

3.1.1

Power-Up Sequence

............................................................................................ 29

3.1.2

Power-Down Sequence

......................................................................................... 30

3.2

Bridge Reset Features

..................................................................................................... 30

3.3

PCI Express Interface

..................................................................................................... 31

3.3.1

External Reference Clock

...................................................................................... 31

3.3.2

Beacon

............................................................................................................ 32

3.3.3

Wake

.............................................................................................................. 32

3.3.4

Initial Flow Control Credits

..................................................................................... 32

3.3.5

PCI Express Message Transactions

.......................................................................... 32

3.4

PCI Bus Interface

........................................................................................................... 33

3.4.1

I/O Characteristics

............................................................................................... 33

3.4.2

Clamping Voltage

................................................................................................ 33

3.4.3

PCI Bus Clock Run

.............................................................................................. 33

3.4.4

PCI Bus External Arbiter

........................................................................................ 34

3.4.5

MSI Messages Generated from the Serial IRQ Interface

.................................................. 34

3.4.6

PCI Bus Clocks

.................................................................................................. 35

3.5

PCI Port Arbitration

........................................................................................................ 36

3.5.1

Classic PCI Arbiter

.............................................................................................. 36

3.6

Configuration Register Translation

....................................................................................... 36

3.7

PCI Interrupt Conversion to PCI Express Messages

.................................................................. 38

3.8

PME Conversion to PCI Express Messages

........................................................................... 38

3.9

PCI Express to PCI Bus Lock Conversion

.............................................................................. 39

3.10

Two-Wire Serial-Bus Interface

............................................................................................ 40

3.10.1

Serial-Bus Interface Implementation

.......................................................................... 41

3.10.2

Serial-Bus Interface Protocol

................................................................................... 41

3.10.3

Serial-Bus EEPROM Application

.............................................................................. 43

3.10.4

Accessing Serial-Bus Devices Through Software

........................................................... 45

3.11

Advanced Error Reporting Registers

.................................................................................... 45

3.12

Data Error Forwarding Capability

........................................................................................ 45

3.13

General-Purpose I/O Interface

............................................................................................ 46

3.14

Set Slot Power Limit Functionality

....................................................................................... 46

3.15

PCI Express and PCI Bus Power Management

........................................................................ 46

3.16

Auto Pre-Fetch Agent

...................................................................................................... 47

Classic PCI Configuration Space

.......................................................................................... 48

4.1

Vendor ID Register

......................................................................................................... 49

4.2

Device ID Register

......................................................................................................... 49

4.3

Command Register

........................................................................................................ 50

4.4

Status Register

............................................................................................................. 51

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