XIO2001 datasheet(40/131 Pages) TI

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CLK

FRAME

LOCK

IRDY

3.10 Two-Wire Serial-Bus Interface

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

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Figure 3-11. Continuing a Locked Sequence

Because PCI Express does not have a unique locked-memory write request packet, all PCI Express

memory write requests that are received while the bridge is locked are considered part of the locked

sequence and are transmitted to PCI as locked-memory write transactions.

The bridge terminates the locked sequence when an unlock message is received from PCI Express and

all previous locked transactions have been completed.

Figure 3-12. Terminating a Locked Sequence

In the erroneous case that a normal downstream memory read request is received during a locked

sequence, the bridge responds with an unsupported request completion status. Note that this condition

must never occur, because the PCI Express Specification requires the root complex to block normal

memory read requests at the source. All locked sequences that end successfully or with an error condition

must be immediately followed by an unlock message. This unlock message is required to return the bridge

to a known unlocked state.

The bridge provides a two-wire serial-bus interface to load subsystem identification information and

specific register defaults from an external EEPROM. The serial-bus interface signals (SDA and SCL) are

shared with two of the GPIO terminals (3 and 4). If the serial bus interface is enabled, then the GPIO3 and

GPIO4 terminals are disabled. If the serial bus interface is disabled, then the GPIO terminals operate as

described in Section 3.13.

Feature/Protocol Descriptions

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