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XIO2001 датащи(PDF) 23 Page - Texas Instruments |
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XIO2001 датащи(HTML) 23 Page - Texas Instruments |
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23 / 131 page ![]() XIO2001 PCI Express™ to PCI Bus Translation Bridge www.ti.com SCPS212B – MAY 2009 – REVISED JULY 2009 Table 2-7. PCI Express Terminals (continued) ZGU ZAJ I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # TYPE TYPE RAIL PARTS TXP G13 H13 DO HS DIFF VDD_15 High-speed transmit pair. TXP and TXN Series TXN G12 G13 OUT comprise the differential transmit pair for the capacitor single PCI Express lane supported. WAKE M13 L12 O LV VDD_33_ Wake is an active low signal that is driven low CMOS COMBIO to reactivate the PCI Express link hierarchy’s main power rails and reference clocks. – Note: Since WAKE is an open-drain output buffer, a system side pullup resistor is required. Table 2-8. PCI System Terminals ZGU ZAJ I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # TYPE TYPE RAIL PARTS AD31 N05 N05 I/O PCI Bus PCIR PCI address data lines AD30 N04 L05 AD29 L05 M05 AD28 M05 N04 AD27 N03 N03 AD26 M04 L04 AD25 N02 M04 AD24 M03 N02 AD23 L04 L03 AD22 M02 M02 AD21 L03 N01 AD20 M01 L02 AD19 L02 K02 AD18 L01 M01 AD17 K02 K03 AD16 K01 L01 – AD15 E01 F02 AD14 E02 E03 AD13 E03 E01 AD12 D01 E02 AD11 D02 D01 AD10 C01 C01 AD9 C02 D02 AD8 D03 B01 AD7 C03 A01 AD6 B02 B03 AD5 C04 C03 AD4 A02 A02 AD3 B03 A03 AD2 B04 C04 AD1 A03 C05 AD0 C05 B04 C/BE[3] N01 M03 I/O PCI Bus PCIR PCI command byte enables C/BE[2] J03 K01 – C/BE[1] F02 F03 C/BE[0] B01 C02 CLK F03 F01 I PCI Bus PCIR PCI clock input. This is the clock input to the – PCI bus core. CLKOUT0 B05 B05 O PCI Bus PCIR PCI clock outputs. These clock outputs are CLKOUT1 B06 B06 used to clock the PCI bus. If the bridge PCI CLKOUT2 A07 B07 bus clock outputs are used, then CLKOUT6 CLKOUT3 B07 A07 – must be connected to the CLK input. CLKOUT4 A09 A08 CLKOUT5 A10 A10 CLKOUT6 B11 C10 DEVSEL H02 H02 I/O PCI Bus PCIR Pullup PCI device select resistor per PCI spec Submit Documentation Feedback Overview 23 |
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