XIO2001 datasheet(74/131 Pages) TI

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4.54 Link Status Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

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Table 4-29. Link Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

CPM_EN

Clock Power Management Enable. This bit is used to enable the bridge to use CLKREQ

for clock power management

0 = Clock Power Management is disabled. CLKREQ is held low.

1 = Clock Power Management is enabled and the bridge is permitted to use the

CLKREQ signal to allow the REFCLK input to be stopped

The default value for this is bit is determined by bit 23 (CPM_EN_DEF_OVRD) in

the general control register (offset D4h, see Section 4.65).

Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets

and an extra TS2 when exiting from L1 prior to entering to L0.

0 = Normal synch (default)

1 = Extended synch

CCC

Common clock configuration. When this bit is set, it indicates that the bridge and the

device at the opposite end of the link are operating with a common clock source. A value

of 0b indicates that the bridge and the device at the opposite end of the link are operating

with separate reference clock sources. The bridge uses this common clock configuration

information to report the L0s and L1 exit latencies.

0 = Reference clock is asynchronous (default)

1 = Reference clock is common

Retrain link. This bit has no function and is read-only 0b.

Link disable. This bit has no function and is read-only 0b.

RCB

Read completion boundary. This bit is an indication of the RCB of the root complex. The

state of this bit has no affect on the bridge, since the RCB of the bridge is fixed at 128

bytes.

0 = 64 bytes (default)

1 = 128 bytes

RSVD

Reserved. Returns 0b when read.

1:0

ASLPMC

Active state link PM control. This field enables and disables the active state PM. The

default value for this is bit is determined by bits 29:28 (ASPM_CTRL_DEF_OVRD) in the

general control register (offset D4h, see Section 4.65).

00 = Active state PM disabled (default)

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

The link status register indicates the current state of the PCI Express link. See Table 4-30 for a complete

description of the register contents.

PCI register offset:

82h

Read-only

Default value:

X011h

BIT NUMBER

RESET STATE

Table 4-30. Link Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

LABW

Link autonomous bandwidth status. This bit has no function and is read-only 0b.

LBWM

Link bandwidth management status. This bit has no function and is read-only 0b.

DLLLA

Data link layer link active. This bit has no function and is read-only 0b.

SCC

Slot clock configuration. This bit indicates that the bridge uses the same physical reference

clock that the platform provides on the connector. If the bridge uses an independent clock

irrespective of the presence of a reference on the connector, then this bit must be cleared.

0 = Independent 125-MHz reference clock is used

1 = Common 100-MHz reference clock is used

Classic PCI Configuration Space

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