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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001 датащи(PDF) 25 Page - Texas Instruments |
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XIO2001 датащи(HTML) 25 Page - Texas Instruments |
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25 / 131 page  XIO2001 PCI Express™ to PCI Bus Translation Bridge www.ti.com SCPS212B – MAY 2009 – REVISED JULY 2009 Table 2-9. JTAG Terminals ZGU ZAJ I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # TYPE TYPE RAIL PARTS JTAG_TCK M12 N12 I LV VDD_33 JTAG test clock input. This signal provides the CMOS clock for the internal TAP controller. Optional Note: This terminal has an internal active pullup pullup resistor. The pullup is active at all resistor times. Note: This terminal should be tied to ground or pulled low if JTAG is not required. JTAG_TDI N12 L10 I LV VDD_33 JTAG test data input. Serial test instructions CMOS and data are received on this terminal. Optional Note: This terminal has an internal active pullup pullup resistor. The pullup is active at all resistor times. Note: This terminal can be left unconnected if JTAG is not required. JTAG_TDO M11 N11 O LV VDD_33 JTAG test data output. This terminal the serial CMOS output for test instructions and data. – Note: This terminal can be left unconnected if JTAG is not required. JTAG_TMS L10 L11 I LV VDD_33 JTAG test mode select. The signal received at CMOS JTAG_TMS is decoded by the internal TAP controller to control test operations. Optional Note: This terminal has an internal active pullup pullup resistor. The pullup is active at all resistor times. Note: This terminal can be left unconnected if JTAG is not required. JTAG_TRS L09 L09 I LV VDD_33 JTAG test reset. This terminal provides T CMOS Optional for asynchronous initialization of the TAP controller. Optional Note: This terminal has an internal active pullup pullup resistor. The pullup is active at all resistor times. Note: This terminal should be tied to ground or pulled low if JTAG is not required. Table 2-10. Miscellaneous Terminals ZGU ZAJ I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # TYPE TYPE RAIL PARTS CLKRUN_E A13 C11 I LV VDD_33 Clock run enable N CMOS 0 = Clock run support disabled Optional 1 = Clock run support enabled pullup resistor Note: The CLKRUN_EN input buffer has an internal active pulldown. This pulldown is active at all times. EXT_ARB_ C10 A12 I LV VDD_33 External arbiter enable EN CMOS 0 = Internal arbiter enabled Optional pullup 1 = External arbiter enabled resistor Note: The EXT_ARB_EN input buffer has an internal active pulldown. This pulldown is active at all times. Submit Documentation Feedback Overview 25 |
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