XIO2001 datasheet(77/131 Pages) TI

77 / 131 page

4.59 GPIO Control Register

4.60 GPIO Data Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

www.ti.com

SCPS212B – MAY 2009 – REVISED JULY 2009

Table 4-32. Serial-Bus Control and Status Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

0(1)

ROM_ERR

RCU

Serial EEPROM load error. This bit is set when an error occurs while downloading registers

from serial EEPROM.

0 = No error

1 = EEPROM load error

This register controls the direction of the five GPIO terminals. This register has no effect on the behavior

of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0

(CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL). See Table 4-33 for a complete

description of the register contents.

PCI register offset:

B4h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4-33. GPIO Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:5

RSVD

Reserved. Return 000h when read.

4(1)

GPIO4_DIR

GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.

0 = Input (default)

1 = Output

3(1)

GPIO3_DIR

GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.

0 = Input (default)

1 = Output

2(1)

GPIO2_DIR

GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.

0 = Input (default)

1 = Output

(1)

GPIO1_DIR

GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.

0 = Input (default)

1 = Output

0(1)

GPIO0_DIR

GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.

0 = Input (default)

1 = Output

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

This register reads the state of the input mode GPIO terminals and changes the state of the output mode

GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The

secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL).

The default value at power up depends on the state of the GPIO terminals as they default to

general-purpose inputs. See Table 4-34 for a complete description of the register contents.

PCI register offset:

B6h

Read-only, Read/Write

Default value:

00XXh

Submit Documentation Feedback

Classic PCI Configuration Space

XIO2001 датащи(PDF) 77 Page - Texas Instruments

XIO2001 датащи(HTML) 77 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL