H838532H datasheet(234/508 Pages) RENESAS

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Section 9 Timers

Rev. 1.00 May 30, 2008 Page 214 of 484

REJ09B0436-0100

(3) Clock Output

Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin

TMOW. Nine different clock output signals can be selected by means of bits TMA7 to TMA5 in

TMA and bit CWOS in CWOSR. The system clock divided by 32, 16, 8, or 4 can be output in

active mode and sleep mode. A 32.768 kHz or 38.4 kHz signal divided by 32, 16, 8, or 4 can be

output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. The 32.768

kHz or 38.4 kHz clock is output in all modes except the reset state.

9.2.4

Timer A Operation States

Table 9.4 summarizes the timer A operation states.

Table 9.4

Timer A Operation States

Operation Mode

Reset

Active

Sleep

Watch

Sub-

active

Sub-

sleep

Standby

Module

Standby

TCA Interval

Reset

Functions Functions Halted

Halted

Clock time base

Reset

Functions Functions Functions Functions Functions Halted

Halted

TMA CWOSR

Reset

Functions Retained

Retained

Functions Retained

Retained

Note:

When the real-time clock time base function is selected as the internal clock of TCA in

active mode or sleep mode, the internal clock is not synchronous with the system clock, so

it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/

φ (s) in

the count cycle.

9.2.5

Application Note

When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of

the timer mode register A (TMA) cannot be rewritten.

Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)

of the timer mode register A (TMA).

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